Projects Gallery

Defense Presentations

Verification of the MDIO Interface Protocol

Verification of the MDIO Interface Protocol

Shashank Chakilam
May 12, 2025
4:00 PM
AURORA⁺
FEATURED

AURORA

Aaron S, Bisum S , Ratish S
May 15, 2025
1:05 PM PST

ASIC Implementation of a Pipelined 16 Bit CPU

ASIC Implementation of a Pipelined 16 Bit CPU

Herminio TJ Santos
May 13, 2025
12:30 PM PST
NBA⁺ SRAM Project

NBA SRAM Project

Aaron S, Bisum S, Nick D
May 15, 2025
2:01 PM PST

ASIC Implementation of a PID Controller

ASIC Implementation of a PID Controller

Nipuna Rajapaksha
May 9, 2025
2:00 PM PST

ASIC Implementation of BLAKE2s Cryptographic Hash Function

ASIC Implementation of BLAKE2s Cryptographic Hash Function

Ganavi Murthy
May 13, 2025
1:00 PM

Asic Implementation of Sobel Edge Detection Filter

Asic Implementation of Sobel Edge Detection Filter

Xuewen Jiang
May 16, 2025
11:00 AM

ASIC Implementation of NVDLA: Understanding NVIDIA Deep Learning Accelerator Architecture

ASIC Implementation of NVDLA: Understanding NVIDIA Deep Learning Accelerator Architecture

Yosabet Kassie, Kavan Bhatt
May 13, 2025
3:30 PM

Optimal Buffer Insertion under Electromigration Effect in Nanoscale Technologies

Optimal Buffer Insertion under Electromigration Effect in Nanoscale Technologies 

Moiz Ahmed Khan
May 16, 2025
4:00 PM

VERIFICATION OF AMBA AHB-APB BRIDGE USING UVM

VERIFICATION OF AMBA AHB-APB BRIDGE USING UVM

Arok Lijo Joe Victar
May 16, 2025
3:00 PM

Verification of SPI protocol using Synopsys VCS

Verification of SPI protocol using Synopsys VCS

Sandeesh Reddy Polamreddy
May 16, 2025
12:00 PM

SweRV EH1 Core Verification

SweRV EH1 Core Verification

Mohammed Ata Ur Rahman
May 16, 2025
2:00 PM
ASIC Implementation of NVIDIA Deep Learning Accelerator

ASIC Implementation of NVIDIA Deep Learning Accelerator

HARIKA KUMBHAM
May 16, 2025
1:00 PM

Physical Design Implementation of ORCA TOP using 28nm technology

Physical Design Implementation of ORCA TOP using 28nm technology

Pavan Kalyan Gorityala
May 16, 2025
10:00 AM

ASIC Implementation of Out of Order Processor

ASIC Implementation of Out of Order Processor

Sahana B Vijayakumar
May 21, 2025
10:30 AM
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Nano-Electronics & Computing Research Laboratory at San Francisco State University focuses on designing reliable, energy efficient, high performance computing circuits in emerging nanotechnologies.

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